4-bit Carry Ripple Adder Verilog code

Theory:

Assume you want to add two operands A and B.
                      Cin
               A3 A2 A1 A0
            + B3 B2 B1 B0
 Cout      S3 S2 S1 S0

From the example above it can be seen that we are adding 3 bits at a time sequentially until
all bits are added. A full adder is a combinational circuit that performs the arithmetic sum of three
input bits: augends Ai, addend Bi and carry in Cin from the previous adder. Its results contain the

sum Si and the carry out, Cout to the next stage.

So to design a 4-bit adder circuit we start by designing the 1 –bit full adder then connecting the
four 1-bit full adders to get the 4-bit adder as shown in the diagram above.For the 1-bit full adder,
the design begins by drawing the Truth Table for the three input and the corresponding output SUM
and  CARRY.  The  Boolean  Expression  describing  the  binary  adder  circuit  is  then  deduced.  The
binary full adder is a three input combinational circuit which satisfies the truth table below.

The Boolean equations of a full adder are given by:

Verilog Module for 4-bit Carry Ripple Adder:

module ripple_carry_adder(a, b, cin, sum, cout);
input [03:0] a;
input [03:0] b;
input cin;
output [03:0] sum;
output cout;
wire [2:0]c;
fulladd a1(a[0],b[0],cin,sum[0],c[0]);
fulladd a2(a[1],b[1],c[0],sum[1],c[1]);
fulladd a3(a[2],b[2],c[1],sum[2],c[2]);
fulladd a4(a[3],b[3],c[2],sum[3],cout);
endmodule
module fulladd(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
assign sum=(a^b^cin);
assign cout=((a&b)|(b&cin)|(a&cin));

endmodule

Test bench for Verilog Module :

module test_ripple_adder_4bit;
// Inputs
reg [3:0] A;
reg [3:0] B;
reg Cin;
// Outputs
wire [3:0] Sum;
wire Cout;
// Instantiate the Unit Under Test (UUT)
ripple_adder_4bit uut (.Sum(Sum),.Cout(Cout),.A(A),.B(B),.Cin(Cin));
initial begin
// Initialize Inputs
A = 0;B = 0;Cin = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
A=4'b0001;B=4'b0000;Cin=1'b0;
#100
A=4'b1010;B=4'b0011;Cin=1'b0;
#100
A=4'b1101;B=4'b1010;Cin=1'b1;
End
initial begin
$monitor("time=",$time,, "A=%b B=%b Cin=%b : Sum=%b Cout=%b",A,B,Cin,Sum,Cout);

end