Kogge-Stone adder verilog code

KOGGE-STONE  ADDER:

The KoggeStone has low logic depth, high node count, and minimal fan out. While a high node count implies a larger area, the low logic depth  and  minimal  fanout  allow  faster performance
There  are  mainly  three  computational stages in KoggeStone Adder. They are:
1. Preprocessing
2. Carry generation network
3. Post processing

Preprocessing Stage:
Preprocessing  is  the  first  stage  where  the generate and propagate signals of all the input pairs  of  signals A  and  B  are  generated separately for each bit. The logical equations of the propagate and generate signals are given by the following equations:

Pi= Aix or Bi ...(1)
Gi= Aiand Bi ...(2)

Carry Generation Stage:
Carry generation is the second stage of the KSA. At this stage the carries of all the bits are generated separately for each bit. They are divided into smaller pieces and this overall process is carried out in parallel for all the bits. Carry generate and Carry propagate bits are used as intermediate signals and their logical
equations are given as follows:

CPi:j =Pi:k + 1 and Pk:j ...(3)
CGi:j =Gi:k + 1 or (Pi:k + 1 and Gk:j)...(4)

Post Processing Stage:
This is the final step or stage of the KSA which is  common  for  all  types  of  adders,  i.e.,calculation of summation of the bits given by the logical Equations (5) and (6):

Ci–1 = (Pi and Cin) or Gi ...(5)
Si= Pix or Ci–1 ...(6)

Schematic of the 4 Bit KoggeStone Adder:

4 Bit KoggeStone Adder Verilog code:

module ksa4(input [3:0]a,
input [3:0]b,
input cin,
output [3:0]sum,

output carryout
    );
wire [3:0] p,g,cp,cg,ccg,ccp,c;

assign p=a^b;
assign g=a&b;

assign cg[0]=(g[0]);
assign cp[0]=(p[0]);

assign cg[1]=(p[1]&g[0])|g[1];
assign cp[1]=(p[1]&p[0]);

assign cg[2]=(p[2]&g[1])|g[2];
assign cp[2]=p[2]&p[1];

assign cg[3]=(p[3]&g[2])|g[3];
assign cp[3]=p[3]&p[2];

assign ccg[0]=cg[0];
assign ccp[0]=cp[0];

assign ccg[1]=cg[1];
assign ccp[1]=cp[1];

assign ccg[2]=(cp[2]&cg[0])|cg[2];
assign ccp[2]=cp[2]&cp[0];

assign ccg[3]=(cp[3]&cg[1])|cg[3];
assign ccp[3]=cp[3]&cp[1];

assign c=ccg;
assign sum[0]=p[0]^cin;
assign sum[1]=p[1]^c[0];
assign sum[2]=p[2]^c[1];
assign sum[3]=p[3]^c[2];
assign carryout=c[3];


endmodule