Kogge-Stone adder verilog code

KOGGE-STONE  ADDER:

The KoggeStone has low logic depth, high node count, and minimal fan out. While a high node count implies a larger area, the low logic depth  and  minimal  fanout  allow  faster performance
There  are  mainly  three  computational stages in KoggeStone Adder. They are:
1. Preprocessing
2. Carry generation network
3. Post processing

Preprocessing Stage:
Preprocessing  is  the  first  stage  where  the generate and propagate signals of all the input pairs  of  signals A  and  B  are  generated separately for each bit. The logical equations of the propagate and generate signals are given by the following equations:

Pi= Aix or Bi ...(1)
Gi= Aiand Bi ...(2)

Carry Generation Stage:
Carry generation is the second stage of the KSA. At this stage the carries of all the bits are generated separately for each bit. They are divided into smaller pieces and this overall process is carried out in parallel for all the bits. Carry generate and Carry propagate bits are used as intermediate signals and their logical
equations are given as follows:

CPi:j =Pi:k + 1 and Pk:j ...(3)
CGi:j =Gi:k + 1 or (Pi:k + 1 and Gk:j)...(4)

Post Processing Stage:
This is the final step or stage of the KSA which is  common  for  all  types  of  adders,  i.e.,calculation of summation of the bits given by the logical Equations (5) and (6):

Ci–1 = (Pi and Cin) or Gi ...(5)
Si= Pix or Ci–1 ...(6)

Schematic of the 4 Bit KoggeStone Adder:

4 Bit KoggeStone Adder Verilog code:

module ksa4(input [3:0]a,
input [3:0]b,
input cin,
output [3:0]sum,

output carryout
    );
wire [3:0] p,g,cp,cg,ccg,ccp,c;

assign p=a^b;
assign g=a&b;

assign cg[0]=(g[0]);
assign cp[0]=(p[0]);

assign cg[1]=(p[1]&g[0])|g[1];
assign cp[1]=(p[1]&p[0]);

assign cg[2]=(p[2]&g[1])|g[2];
assign cp[2]=p[2]&p[1];

assign cg[3]=(p[3]&g[2])|g[3];
assign cp[3]=p[3]&p[2];

assign ccg[0]=cg[0];
assign ccp[0]=cp[0];

assign ccg[1]=cg[1];
assign ccp[1]=cp[1];

assign ccg[2]=(cp[2]&cg[0])|cg[2];
assign ccp[2]=cp[2]&cp[0];

assign ccg[3]=(cp[3]&cg[1])|cg[3];
assign ccp[3]=cp[3]&cp[1];

assign c=ccg;
assign sum[0]=p[0]^cin;
assign sum[1]=p[1]^c[0];
assign sum[2]=p[2]^c[1];
assign sum[3]=p[3]^c[2];
assign carryout=c[3];


endmodule

4-bit Carry Ripple Adder Verilog code

Theory:

Assume you want to add two operands A and B.
                      Cin
               A3 A2 A1 A0
            + B3 B2 B1 B0
 Cout      S3 S2 S1 S0

From the example above it can be seen that we are adding 3 bits at a time sequentially until
all bits are added. A full adder is a combinational circuit that performs the arithmetic sum of three
input bits: augends Ai, addend Bi and carry in Cin from the previous adder. Its results contain the

sum Si and the carry out, Cout to the next stage.

So to design a 4-bit adder circuit we start by designing the 1 –bit full adder then connecting the
four 1-bit full adders to get the 4-bit adder as shown in the diagram above.For the 1-bit full adder,
the design begins by drawing the Truth Table for the three input and the corresponding output SUM
and  CARRY.  The  Boolean  Expression  describing  the  binary  adder  circuit  is  then  deduced.  The
binary full adder is a three input combinational circuit which satisfies the truth table below.

The Boolean equations of a full adder are given by:

Verilog Module for 4-bit Carry Ripple Adder:

module ripple_carry_adder(a, b, cin, sum, cout);
input [03:0] a;
input [03:0] b;
input cin;
output [03:0] sum;
output cout;
wire [2:0]c;
fulladd a1(a[0],b[0],cin,sum[0],c[0]);
fulladd a2(a[1],b[1],c[0],sum[1],c[1]);
fulladd a3(a[2],b[2],c[1],sum[2],c[2]);
fulladd a4(a[3],b[3],c[2],sum[3],cout);
endmodule
module fulladd(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
assign sum=(a^b^cin);
assign cout=((a&b)|(b&cin)|(a&cin));

endmodule

Test bench for Verilog Module :

module test_ripple_adder_4bit;
// Inputs
reg [3:0] A;
reg [3:0] B;
reg Cin;
// Outputs
wire [3:0] Sum;
wire Cout;
// Instantiate the Unit Under Test (UUT)
ripple_adder_4bit uut (.Sum(Sum),.Cout(Cout),.A(A),.B(B),.Cin(Cin));
initial begin
// Initialize Inputs
A = 0;B = 0;Cin = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
A=4'b0001;B=4'b0000;Cin=1'b0;
#100
A=4'b1010;B=4'b0011;Cin=1'b0;
#100
A=4'b1101;B=4'b1010;Cin=1'b1;
End
initial begin
$monitor("time=",$time,, "A=%b B=%b Cin=%b : Sum=%b Cout=%b",A,B,Cin,Sum,Cout);

end